As DRAM (dynamic random access memory) devices have become more finely structured, both the area of such devices and the diameter of contacts used on these devices have been reduced. Despite a reduction of both the area and the diameter in the horizontal direction, however, this fine structure does not effect the structural characteristics of a DRAM in the vertical direction. Accordingly, contacts must be both fine and long.
Referring to FIG. 1, a device isolation region (not shown) defining an active region and an inactive region is formed in a semiconductor substrate 10. A first conductive layer (not shown), a second conductive layer (not shown), and a gate mask 16 are formed over a semiconductor substrate 10 in the active region with a gate oxide layer (not shown) interposed between these layers and the substrate 10. The first and second conductive layers are then etched using the gate mask 16 as an etching mask to form a gate electrode of a double layer structure including first and second gate electrode portions 12 and 14.
After or before the formation of the insulating layer spacer 16, impurity ions are implanted to form a source/drain region (not shown) in the semiconductor substrate 10 outside of the area covered by the gate electrode 12 and 14. A first interlayer insulating film 20 is then formed over the semiconductor substrate 10 and the gate electrode 12 and 14.
The first insulating film 20 is penetrated by a first contact hole 21, and the resulting contact hole 21 is filled with a conductive material to form a contact pad 22 that is electrically connected to the source/drain region.
A second interlayer insulating film 24, including an embedded bit line 26, is then formed over the first interlayer insulating film 20. The second insulating film 24 is etched to form a second contact hole 28 that exposes a top surface of the contact pad 22. A silicon nitride layer spacer 30 is then formed on the sidewalls of the contact hole 28.
The second contact hole 28 is then filled with a conductive material to form a buried contact (BC) 32 that electrically connects a lower capacitor electrode to the contact pad 22. In order to make this electrical connection to the buried contact 32, a conductive layer (not shown) is formed over the second interlayer insulating film 24. The conductive layer is then patterned to form the lower capacitor electrode 34.
In the DRAM device of a capacitor over bit line (COB) structure, as described above, the buried contact 32 becomes fine and long. Furthermore, as shown in FIG. 1, the spacers 30 formed on the sidewalls of a contact hole may reduce the contact area between the contact pad 22 and the buried contact 32. As a result, the resistance between the contact pad 22 and the buried contact 32 increases, thereby slowing down the operation speed of the DRAM and potentially making an electrical open circuit, if the resistance is high enough.